1. Technical Field
The present invention relates to a test apparatus, a test method, and a computer readable medium.
2. Related Art
When testing a plurality of semiconductor chips en masse on a semiconductor wafer, a probe card is used that has a large number of bumps corresponding to the test pads of the semiconductor chip.
Since the test pads and the bumps are extremely small, in order to accurately align the bumps with the corresponding test pads, alignment marks are formed on both the semiconductor wafer and the probe card, and these alignment marks are used to set the positions of the semiconductor wafer and the probe card, as shown in Patent Documents 1 to 3.    Patent Document 1: Japanese Patent No. 4187718    Patent Document 2: Japanese Patent Application Publication No. H07-231019    Patent Document 3: Japanese Patent Application Publication No. H11-154694
Even when the semiconductor wafer and the probe card are positioned with a high degree of accuracy, misalignment can occur between the test pad and the bumps due to manufacturing errors in the semiconductor wafer, the probe card, or the alignment mark or due to deformation of the semiconductor wafer or the probe card as the result of a temperature change.